1. Field of the Invention
The present invention relates generally to semiconductor manufacturing and, more particularly, to the verification of lithographic printing of shapes used in microelectronic devices.
2. Description of Related Art
Current state of the art lithographic printing processes are able to reproduce consistent polysilicon line widths below 100 nm. As used herein, the term critical dimension (CD) or critical width refers to the smallest dimension of a shape, pattern or feature that can be produced by the lithographic system. However, as the line widths are scaled down, the roughness of the line edges does not scale down similarly. Edge roughness of polysilicon lines is typically on the order of 5 nm, but can have values much higher than that, depending on how the line was formed. Including other causes, total line width variability can increase to above 10 nm. For proper operation, electronic devices incorporating gates are required to control gate length within approximately 8 nm. Edge roughness is therefore one of the primary concerns in controlling channel length for such devices.
Currently, there is no safe method of predicting imaging for such small width polysilicon lines prior to actually constructing a mask, developing wafers, and collecting results. This incurs great expense to the process. Physical measurements generally cannot accurately predict the electrical performance of electronic devices incorporating gates. Examination of simulated wafer images using optical and resist models for fidelity of the image to the desired target shape, sometimes referred to as Optical Rules Checking (ORC), is a step sometimes used for resolution enhancements for small line and gate patterning. Rapid simulation ORC techniques predict the wafer image based on image intensity profiles al selected spaced, but critical, sites along the shape generated during what is known as segmentation or fragmentation, similar to what is used for model-based ORC. Error statistics from these standard ORC techniques are generated using the optical properties computed at sites resulting from the chosen fragmentation scheme for the given data set and lithographic process. For most applications, these are adequate and provide ample image checking. However, in many cases, it has been determined that simulations based on image profiles at these sites are unable to represent adequately the intensity contours computed from a complete and detailed simulation on a dense grid, thereby missing some intra-line variation and many extraneous shapes and unwanted artifacts.
There is a need for an effective method of detecting design geometries whose printability by lithographic processes is at risk. It would be useful to be able to predict device functionality, particularly the potential for catastrophic failure, and to quantify the effectiveness of optical proximity correction (OPC) by classification of areas of the design.